#Modelsim altera tutoral testbench how to
#Modelsim altera tutoral testbench code

#Modelsim altera tutoral testbench how to

The example below shows how to import and use the stop procedure.ДЄ problem with using stop in script-based setups is that it doesnвЂ™t quit the simulation. The simulator treats it like a breakpoint. That may be useful if you want to examine signal values manually or even continue the simulation later. The VHDL stop procedure causes the simulation to pause.

#Modelsim altera tutoral testbench code

However, you can control the Linux exit code value in ModelSim by using the Tcl command exit -code, but thatвЂ™s another story. The wording in the VHDL-2008 standard is вЂњ the value of the STATUS parameter may be used in an implementation defined manner by the host simulatorвЂњ. The problem with using this status code is that what it does depends on the simulator. You would think that the status integer becomes the exit code when called from a Linux shell, but thatвЂ™s not the case, at least not with ModelSim.

ThereвЂ™s the version without any parameters, which is the one I always use, and thereвЂ™s another that takes a status integer as a constant input. As we can see from the code below, it comes in two overloaded flavors. # Errors: 0, Warnings: VHDL finish procedure is defined in the standard ENV package.

# Time: 1 ms Iteration: 0 Instance: /using_finish_tb After the testbench completes, the simulator quits, and at the last line, we are back in the Linux vsim -c -do 'vsim ing_finish_tb run -all' The example below shows a testbench using the finish procedure started in ModelSim batch mode in Linux. If you are using scripts to start the simulation, you want to return control to the calling script after the simulation finishes. By doing so, the finish procedure will behave in the same way as the stop procedure that we will discuss in the next section of this article.ДЄn advantage of using finish is that you can use the default behavior when simulating in batch mode. Fortunately, we can prevent this behavior by adding the вЂњ-onfinish stopвЂќ option to the vsim command, as shown below. If you click Yes, ModelSim is going to quit. If you are running ModelSim in the GUI version, a popup will appear saying вЂњAre you sure you want to finish?вЂќ. Note that finish quits the simulation by default. Replace this line with your testbench logic The code below ends the simulation when we reach the last line of the testbench sequencer process. You have to import вЂњfinishвЂќ from the STD.ENV package, and you have to compile the testbench in VHDL-2008 or newer to use it. The VHDL finish procedure is my favorite way of stopping a VHDL testbench that completes without errors.